1. Field of the Invention
The present invention relates to a method of memory, and more particularly to a method for storing data and information related to data error correction by combining plural memory cells, which can increase memory capacity without extra area penalty.
2. Description of the Prior Art
With digital technology developing, information transmission is not limited by the space any more. Not only far-reaching transmitting on network, data can be also carried about by various memory in portable devices. However, how to assure the data transmitted exactly in transmission procedure becomes a very important job since data has to transmit and convert frequently between different interfaces and storing devices. For various memories often used nowadays, the FIG. 1 refers to their data storing procedure. When inputting a data, an error correction code generator 1 carries on the operation of error correction encoding to the data and generates the redundancy, and then assembles the redundancy to be an error correction code capable of identifying the data. Then, a programming circuit 3 writes data and error correction code into a memory device 5. The error correction code will be used to correct error 7 in the data for assuring that data can be outputted exactly.
In 1965, the cofounder, Gordon Moore, of Intel Corp. predicted that the number of silicon chip transistor had doubled every 18 months, also called “Moore's Law”. The memory capacity has been increased from 8M, 16M in the earlier period to 1024M nowadays, the development of memory capacity can be treated as the best witness of Moore's Law. However, it has to overcome many constrictions for achieving the higher capacity in memory cells. Enterprises have to pay more for developing techniques now.
Generally speaking, the technique of increasing memory capacity can be divided in two ways: one is to increase the number of memory cells and the other is to increase capacity of each memory cell using multilevel technique. For example, the characteristic of a multilevel cell is described by a number of curves representing different logic values. FIG. 2 shows the characteristic of a four-level (2-bit) cell which stores the bits “11”, “10”, “01” and “00” corresponding to different voltage levels. Although the capacity has been doubled, on the other hand, the more differential levels in particular voltage region of memory cells, the more hard to develop techniques. If the growth is limited by value of 2m, it indicates that memories of next generation have to be increased to 8 or even 16 voltage levels for providing 3 bits or 4 bits of each memory cell, respectively. Therefore, the experienced curve of technique development will grow exponentially for getting more voltage levels. The present invention presents an effective grouping of several q-level memory cells with q>2m in order to gaining more memory capacity in a linear manner. It is not only getting more capacity and overcoming the technical difficulties to increase the number of voltage levels in memory cells, but also rendering the present invention having error correction scheme for assuring the veracity of the storing data and improving producing yield and reliability for multilevel memory systems.